The present invention relates generally to data processors, and more specifically to a zero warranty circuit for checking the length of a packed decimal operand which is to be processed by a data path having a bit width different from the length of the operand.
Variable length decimal operands stored in a memory of a data processor are specified by the start address and the length of an operand which are contained in an instruction word and a specified operand is read out of the memory and checked for the validity of the format prior to arithmetic operations. The results of the operations are stored again into the memory. In a high-speed, byte oriented data processor in which the variable length decimal operand is fetched on a byte length basis (either four bytes or eight bytes) as a unit of data. If the length of the fetched operand is indivisible by the bit width of the data path, there is a likelihood of data being fetched which does not form part of the operand. In order to invalidate such undesired data, a masking circuit is provided by which all bits in the insignificant portion of any fetched data are replaced with all zeros before being applied to a verification circuit. If the operand has an odd number of decimal digits including a sign code in its lowest digit position, it must be warranted that the higher decimal digit (four bits) of the highest byte be all zeros. To this end, the prior art zero warranty circuit includes a detector circuit that detects the position of the highest decimal digit by determining the length of the operand and checks for the presence or absence of zeros in the highest decimal digit position indicated by the detector circuit. However, the prior art detector circuit is complex, increasing the hardware of the data processor.